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1CY M18 38
fax id: 2015
PRELIMINARY
CYM1838
128K x 32 Static RAM Module
Features
* High-density 4-megabit SRAM module * High-speed CMOS SRAMs -- Access time of 20 ns * 66-pin, 1.1-inch-square PGA package * Low active power -- 4.0W (max.) * Hermetic SMD technology * TTL-compatible inputs and outputs * Commercial and military temperature ranges a multilayer ceramic substrate. Four chip selects (CS1, CS2, CS3, CS4) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. Writing to each byte is accomplished when the appropriate chip selects (CS) and write enable (WE) inputs are both LOW.Data on the input/output pins (I/OX) is written into the memory location specified on the address pins (A0 through A16). Reading the device is accomplished by taking chip selects LOW while write enable remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the data input/output pins. The data input/output pins remain in a high-impedance state when write enable is LOW or the appropriate chip selects are HIGH.
Functional Description
The CYM1838 is a very high performance 4-megabit static RAM module organized as 128K words by 32 bits. The module is constructed using four 128K x 8 static RAMs mounted onto
Logic Block Diagram
A0 - A16 OE
Pin Configuration
PGA Top View
1 12 I/O8 I/O9 WE2 CS2 GND 23 I/O15 I/O14 I/O13 I/O12 OE GND WE1 I/O7 I/O6 I/O5 I/O4 33 I/O24 I/O25 I/O26 A6 A7 GND A8 A9 I/O16 I/O17 I/O18 44 34 VCC CS4 WE4 I/O27 A3 A4 A5 WE3 CS3 GND I/O19 55 45 I/O31 I/O30 I/O29 I/O28 A0 A1 A2 I/O23 I/O22 I/O21 I/O20 66 1838-2 56
17
WE1 CS1
128K x 8 SRAM
8
I/O0- 7
I/O10 A13 A14 A15 A16
I/O11 A10 A11 A12 VCC CS1 GND I/O3 22
WE2 CS2
128K x 8 SRAM
8
I/O8- 15
WE3 CS3
128K x 8 SRAM
8
I/O16- 23
GND
I/O0
WE4 CS4
128K x 8 SRAM
8
I/O24- 31
I/O1 I/O2
1838-1 11
Selection Guide
1838-20 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) Commercial Military Commercial Military 20 720 720 240 240 1838-25 25 720 720 240 240 240 720 1838-35 35
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 July 1992 - Revised May 16, 1997
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired.) Storage Temperature ................................. -65C to +150C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V
CYM1838
DC Input Voltage ............................................-0.5V to +7.0V
Operating Range
Range Commercial Military Ambient Temperature 0C to +70C -55C to +125C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
1838 Parameter VOH VOL VIH VIL IIX IOZ ICCx32 ICCx16 ICCx8 ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current by 32 Mode VCC Operating Supply Current by 16 Mode VCC Operating Supply Current by 8 Mode Automatic CS Power-Down Current[1] Automatic CS Power-Down Current[1] GND < VI < VCC, VCC = Max. GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, CS < VIL VCC = Max., IOUT = 0 mA, CS < VIL VCC = Max., IOUT = 0 mA, CS < VIL Max. VCC; CS > VIH, Min. Duty Cycle = 100% Max. VCC; CS > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 -20 -10 Min. 2.4 0.4 6.0 0.8 +20 +10 720 480 360 240 40 Max. Unit V V V V A A mA mA mA mA mA
Capacitance[2]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 50 50 Unit pF pF
Notes: 1. A pull-up resistor to V CC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis.
AC Test Loads and Waveforms
R1 481 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255 R1 481 3.0V 90% GND < 5 ns
1838-3
ALL INPUT PULSES 90% 10% < 5 ns
1838-4
10%
(a)
(b)
Equivalent to: OUTPUT
THE EVENIN EQUIVALENT 167 1.73V
2
PRELIMINARY
Switching Characteristics Over the Operating Range [3]
1838-20 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS WRITE tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low CYCLE[6] Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z[5] 20 15 15 1.5 2.0 15 10 2 0 0 10 25 20 20 1.5 2.0 17 12 2 0 0 10 35 30 30 1.5 2.0 25 15 2 0 0 Z[4] Z[4,5] 0 12 CS HIGH to High 0 10 0 15 3 20 10 0 10 0 20 20 3 25 12 0 25 25 3 35 Description Min. Max. 1838-25 Min. Max. 1838-35 Min.
CYM1838
Max.
Unit ns
35 35 15 20 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
15
ns
Switching Waveforms
Read Cycle No. 1
ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1838-5
[7,8]
tRC
Notes: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested. 5. tHZCS and tHZWE are specified with C L = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 7. WEN is HIGH for read cycle. 8. Device is continuously selected, CS = VIL and OE= VIL.
3
PRELIMINARY
Switching Waveforms (continued)
Read Cycle No. 2 [7,9]
CS tACS OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCS DATA VALID tHZOE tHZCS t RC
CYM1838
HIGH IMPEDANCE
1838-6
Write Cycle No. 1 (WE Controlled) [6,10]
tWC ADDRESS tSCS CS tAW tSA WE tSD DATA IN DATA VALID tHZWE DATAI/O DATA UNDEFINED
1838-7
tHA tPWE
tHD
tLZWE HIGH IMPEDANCE
Note: 9. Address valid prior to or coincident with CS transition LOW. 10. Data I/O will be high impedance if OE = VIH.
4
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 2 (CS Controlled) [6,10, 11]
tWC ADDRESS tSA CS tAW tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT HIGH IMPEDANCE DATA UNDEFINED tHD tHA tSCS
CYM1838
1838-8
Note: 11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Truth Table
CSN H L L L OE X L X H WEN X H L H Input/Output High Z Data Out Data In High Z Read Write Deselect Mode Deselect/Power-Down
Ordering Information
Speed (ns) 20 Ordering Code CYM1838HG-20C CYM1838HG-20M CYM1838HG-20MB 25 CYM1838HG-25C CYM1838HG-25M CYM1838HG-25MB 35 CYM1838HG-35C CYM1838HG-35M CYM1838HG-35MB Document #: 38-M-00046-C Package Name HG01 HG01 HG01 HG01 HG01 HG01 HG01 HG01 HG01 Package Type 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module Commercial Military Commercial Military Operating Range Commercial Military
5
PRELIMINARY
Package Diagram
66-Pin PGA Module HG01
CYM1838
PIN 1 1.090MAX.
1.090MAX.
0.320 MAX. 0.180 0.050 .012 .600 0.100 TYP .
11 22 33
44 55 66
1.000TYP.
. 0.100 TYP 1 12 23 34 45 56
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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